AD9577BCPZ-R7 datasheet(41/44 Pages) AD

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Data Sheet

AD9577

Rev. 0 | Page 41 of 44

The AD9577 acts as a standard slave device on the bus. The data

on the SDA pin is eight bits long supporting the 7-bit addresses

plus the R/W bit. The

has 31 subaddresses to enable

the user-accessible internal registers (see

). Therefore, it

interprets the first byte as the device address and the second byte as

the starting subaddress. Auto-increment mode is supported, which

allows data to be read from or written to the starting subaddress

and each subsequent address without manually addressing the

subsequent subaddress. A data transfer is always terminated by

a stop condition. The user can also access any unique subaddress

AD9577

Table 30

Stop and start conditions can be detected at any stage of the data

transfer. If these conditions are asserted out of sequence with

normal read and write operations, they cause an immediate jump

to the idle condition. During a given SCL high period, one start

condition, one stop condition, or a single stop condition followed

by a single start condition should be issued. If an invalid subaddress

is issued, the AD9577 does not issue an acknowledge and returns

to the idle condition. If the highest subaddress is exceeded while

reading back in auto-increment mode, the highest subaddress

issues a no acknowledge, which indicates the end of a read. In a no

acknowledge condition, the SDA line is not pulled low on the ninth

pulse. See Figure 45 and Figure 46 for sample read and write data

transfers, and see Figure 47 for a more detailed timing diagram.

To overwrite any of the default register values, complete the

following steps:

Enable the overwriting of registers by setting EnI2C,

Only write to registers that need modification from their

default value.

After all the registers have been set, a new acquisition is

initiated by toggling NewAcq, Register X0[0] from low to high

to low.

An example set of I2C commands follows. These enable the I2C

registers and program the output frequencies of both PLLs. fPFD

is 25 MHz. A leading W represents a write command.

Table 32. I2C Programming Example Register Writes

Write/Read

Data (Hex)

Operation

Enable I2C registers

AF0

Na = 80 + 10 = 90; fVCO1 = 2.25 GHz

ADV0

Channel 0 divides by 5 × 6 = 30; fOUT0 = 75 MHz

ADV1

Channel 1 divides by 6 × 12 = 72; fOUT1 = 31.25 MHz

BF3

Nb = 80 + 21 = 101; FVCO2 = 2.53832 GHz

BF0

FRAC = 333

BF1

FRAC = 333, MOD = 625

BF2

MOD = 625

ABF0

Power-up SDM, release SDM reset

BP0

Turn on Bleed

BDV0

Channel 2 divides by 2 × 4 = 8; fOUT2 = 317.29 MHz

BDV1

Channel 3 divides by 5 × 16 = 80; fOUT3 = 31.729 MHz

Force new acquisition by toggling NewAcq

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