AD9577BCPZ-R7 datasheet(40/44 Pages) AD

40 / 44 page

AD9577

Data Sheet

Rev. 0 | Page 40 of 44

DEFAULT FREQUENCY MAP AND OUTPUT

FORMATS

The power-up operation (without I2C programming) of the

AD9577 is represented by a default frequency map and output

formats (see Table 31).

Table 31. Default Parameter Values, fPFD = 25 MHz

Parameter

Value

Notes

PLL1

fOUT0 = 156.25 MHz,

fOUT1 = 125 MHz

80 + 20 = 100

FORMAT1

000

OUT0/OUT1 are LVPECL

SyncCh01

PLL2

fOUT2 = 100 MHz,

fOUT3 = 33.333 MHz

80 + 16 = 96

FRAC

MOD

PD_SDM

Bleed

FORMAT2

000

OUT2/OUT3 are LVPECL

SyncCh23

SSCG

FracStep

NumSteps

CkDiv

Control

EnI2C

NewAcq

PDCH0

PDCH1

PDCH2

PDCH3

PDRefOut

PDPLL1

PDPLL2

Parameter

Value

Notes

Margining

These parameters are

applied only when the

MARGIN pin = high

PLL1

fOUT0 = 156.25 MHz,

fOUT1 = 125 MHz

80 + 20 = 100

fOUT0

156.25 MHz

fOUT1

125 MHz

PLL2

fOUT2 = 212.5 MHz,

fOUT3 = 106.25 MHz

80 + 22 = 102

FRAC

MOD

I2C INTERFACE OPERATION

The AD9577 is programmed by a 2-wire, I2C-compatible serial bus

driving multiple peripherals. Two inputs, serial data (SDA) and

serial clock (SCL), carry information between any devices

connected to the bus. Each slave device is recognized by a unique

address. The slave address consists of the 7 MSBs of an 8-bit

word. The 7-bit slave address of the AD9577 is 1000000. The LSB

of the word sets either a read or write operation (see Figure 44).

Logic 1 corresponds to a read operation, and Logic 0

corresponds to a write operation.

To control the device on the bus, do the following protocol.

First, the master initiates a data transfer by establishing a start

condition, defined by a high-to-low transition on SDA while

SCL remains high, which indicates that an address/data stream

follows. All peripherals respond to the start condition and shift

the next eight bits (the 7-bit address and the R/W bit). The bits

are transferred from MSB to LSB. The peripheral that recognizes

the transmitted address responds by pulling the data line low

during the ninth clock pulse, which is known as the acknowledge

bit. All other devices withdraw from the bus at this point and

maintain an idle condition. The idle condition is where the device

monitors the SDA and SCL lines waiting for the start condition

and correct transmitted address. The R/W bit determines the

direction of the data. Logic 0 on the LSB of the first byte means

that the master writes information to the peripheral, and Logic 1

on the LSB of the first byte means that the master reads

information from the peripheral.

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