DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

7

Design Example 1:

Assume design parameters as VIN=12V, VO=3.3V and Io=12A.

Table 1: Design Consideration 1 for synchronous buck converter

Input Voltage, Vin

12V

Output Voltage, Vo

3.3V

Output Current, Io

12A

Assume the output ripple voltage is within

± 1% of Vo. For Vo =3.3V, the output ripple

is limited within,

V

t

V

L

033

.

0

)

(

≤

Δ

. When the output capacitor (C1) is 10uF, the inductor

L1 values for the range of switching frequencies from 100 kHz to 500 kHz are given in

Table: 2 based on equations 3-7.

Table 2: When C1= 10uF

Vin

(V)

Vo

(V)

D

ΔV

L

(V)

fs

(kHz)

C1

(uF)

ΔΙ

L1

(A)

L1

(uH)

fc

(kHz)

12

3.3

0.275

0.033

100

10

0.264

90

5.31

12

3.3

0.275

0.033

200

10

0.528

45.31

7.48

12

3.3

0.275

0.033

300

10

0.792

30.20

9.16

12

3.3

0.275

0.033

400

10

1.056

22.65

10.60

12

3.3

0.275

0.033

500

10

1.32

18.12

11.83

Synchronous Driver Controller: ISL6594D from Intersil:

Based on equation 18 and 19, From ISL6594D driver datasheet, given high-side: tr=26nS,

tf=18nS and source/sink current = 1.25/2A (max). For low-side, trr=18nS, tf=12nS and

source/sink current = 2/3.0 A (max):

Table 4: from Datasheet

High-Side

Rise time

Source Current (A)

Required Qg(on)

Source

26 ns

1.25

32.5nC

Sink

18 ns

2

36nC

Low-Side

Rise time

Source Current (A)

Required Qg(on)

Source

18nS

2

36nC

Sink

12ns

3

36nC