MICRF506BML datasheet(19/42 Pages) MICREL

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Micrel

MICRF506BML/YML

Transceiver Sync/Non-Synchronous Mode

A6..A0

0000000

LNA_by

PA2

PA1

PA0

Sync_en

Mode1

Mode0

Load_en

0000110

Mod_clkS2

Mod_clkS1

Mod_clkS0

BitSync_clkS2

BitSync_clkS1

BitSync_clkS0

BitRate_clkS2

0000111

BitRate_clkS1

BitRate_clkS0

RefClk_K5

RefClk_K4

RefClk_K3

RefClk_K2

RefClk_K1

RefClk_K0

Sync_en

State

Comments

Rx: Bit

synchronization off

Transparent reception of

data

Tx: DataClk pin off

Transparent transmission

of data

Rx: Bit

synchronization on

Bit-clock is generated by

transceiver

Tx: DATACLK pin on

Bit-clock is generated by

transceiver

When Sync_en = 1, it will enable the bit

synchronizer in receive mode. The bit synchronizer

clock needs to be programmed, see chapter Bit

synchronizer. The synchronized clock will be set out

on pit DATACLK.

In transmit mode, when Sync_en = 1, the clock

signal on pin DATACLK is a programmed bit rate

clock. Now the transceiver controls the actual data

rate. The data to be transmitted will be sampled on

rising edge of DATACLK. The micro controller can

therefore use the negative edge to change the data

to be transmitted. The clock used for this purpose,

BITRATE_CLK, is programmed in the same way as

the modulator clock and the bit synchronizer clock:

)

XCO

BITRATE_CL

Refclk_K

BitRate_cl

where:

fBITRATE_CLK: The clock frequency used to

control the bit rate, should be equal to the bit

rate (bit rate of 20 kbit/sec requires a clock

requency of 20kHz)

fXCO: Crystal oscillator frequency

Refclk_K: 6 bit divider, values between 1

and 63

BitRate_clkS:

Bit

rate

setting,

values

between 0 and 6

Data Interface

The MICRF506 interface can be divided in to two

separate interfaces, a “programming interface” and a

“Data interface”. The “programming interface” has a

three wire serial programmable interface and is

described in chapter Programming.

The “data interface” can be programmed to sync-

/non-synchronous mode. In synchronous mode the

MICRF506 is defined as “Master” and provides a

data clock that allows users to utilize low cost micro

controller reference frequency.

The data interface is defined in such a way that all

user actions should take place on falling edge and is

illustrated Figure 9 and 10. The two figures illustrate

the relationship between DATACLK and DATAIXO

in receive mode and transmit mode.

MICRF506 will present data on rising edge and the

“USER” sample data on falling edge in receive

mode.

DATAIXO

DATACLK

Figure 10. Data interface in Receive Mode

The User presents data on falling edge and

MICRF506 samples on rising edge in transmit mode.

DATAIXO

DATACLK

Figure 11. Data interface in Transmit Mode

When entering transmit mode it is important to keep

DATAIXO in tri-state from the time Tx-mode is

entered until user starts sending data. The data is

provided directly to the modulation circuit and

violation of this may/will cause abnormal behavior.

Depending upon the chosen FSK modulation, some

sort of encoding might be needed. The different

modulation types and encoding is described in

chapter Frequency modulation.

July 2006

M9999-092904

+1 408-944-0800

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