MICRF506BML datasheet(18/42 Pages) MICREL

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Micrel

MICRF506BML/YML

Charge Pump

A6..A0

0000010

CP_HI

SC_by

‘0’

PA_by OUTS3

OUTS2

OUTS1

July 2006

M9999-092904

+1 408-944-0800

The charge pump current can be set to either 125µA

or 500µA by CP_HI (‘1’ → 500µA). This will affect

the loop filter component values, see “PLL Filter”

section. In most cases, the low current is best suited.

For applications using phase detector frequency and

high PLL bandwidth, the 500µA can be a better

choice.

PLL Filter

The design of the PLL filter will strongly affect the

performance of the frequency synthesizer. The PLL

filter is kept externally for flexibility. Input parameters

when designing the loop filter for the MICRF506 are

mainly the modulation method and the bit rate.

These choices will also affect the switching time and

phase noise.

The frequency modulation can be done in two

different ways with the MICRF506, either by VCO

modulation or by modulation with the internal

dividers (see chapter Frequency modulation for

further details). In the first case, the PLL needs to

lock on a new carrier frequency for every new data

bit. Now the PLL bandwidth needs to be adequately

high. It is recommended to use a third order filter to

suppress the phase detector frequency, as this is

not suppressed as much as when doing modulation

on the VCO with a lower bandwidth filter.

A schematic for a second (R2=0 and C3=NC) and

third order loop filter is shown in Figure 8.

Pin 27

CP_OUT

Pin 29

VARIN

Figure 8. Second and Third Order Loop Filter

Table 9 shows three different loop filters, the two first

for VCO modulation and the last one for modulation

using the internal dividers. The component values

are calculated with RF frequency = 434MHz, VCO

gain = 32MHz/V and charge pump current = 125µA.

Other settings are shown in the table. The varactor

pin capacitance (pin 29) of 5pF does not influence

on the component values for the two filters with

lowest bandwidth.

Baud Rate

(kbaud/sec)

PLL

(kHz)

Phase

Margin(˚)

Phase

Detector

Freq.

(kHz)

VCO

>38.4

0.8

100

10nF

100nF 6.2kΩ

VCO

>125

3,2

100

680pF 6.8nF

22kΩ

Divider

<20

500

150pF

10nF

18kΩ 82kΩ

4.7pF

Table 9. Loop Filter Components Values

Lock Detect

A6..A0

0000001

Modulation1

Modulation0

‘0’

RSSI_en

LD_en

PF_FC1

PF_FC0

A lock detector can be enabled by setting LD_en

= 1. When pin LD is high, it indicates that the

PLL is in lock.

Modes of Operation

A6..A0

0000000

LNA_by

PA2

PA1

PA0

Sync_en

Mode1

Mode0

Load_en

Mode1

Mode0

State

Comments

Power down

Keeps register configuration

Standby

Only crystal oscillator running

Receive

Full receive

Transmit

Full transmit ex PA state

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