R5F5630ACDFB datasheet(3/165 Pages) RENESAS

3 / 165 page

R01DS0060EJ0100 Rev.1.00

Page 3 of 168

Sep 13, 2011

RX630 Group

1. Overview

Interrupt

Interrupt control unit

(ICUb)

 Peripheral function interrupts: 180 sources

 External interrupts: 16 (pins IRQ0 to IRQ15)

 Software interrupts: One source

 Non-maskable interrupts: 6 sources

 Sixteen levels specifiable for the order of priority

External bus extension

 The external address space can be divided into eight areas (CS0 to CS7), each with

independent control of access settings.

Capacity of each area: 16 Mbytes (CS0 to CS7)

A chip-select signal (CS0# to CS7#) can be output for each area.

Each area is specifiable as an 8-, 16- or 32-bit bus space

The data arrangement in each area is selectable as little or big endian (only for data).

 Bus format: Separate bus, multiplex bus

 Wait control

 Write buffer facility

DMA

DMA controller

(DMACA)

 4 channels

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: Software trigger, external interrupts, and interrupt requests from

peripheral functions

Data transfer controller

(DTCa)

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: External interrupts and interrupt requests from peripheral functions

I/O ports

Programmable I/O ports

 177-pin TFLGA (in planning), 176-pin LFBGA (in planning), 176-pin LQFP

I/O pins: 148

Input pin: 1

Pull-up resistors: 148

Open-drain outputs: 148

5-V tolerance: 54

 145-pin TFLGA (in planning), 144-pin LQFP

I/O pins: 117

Input pin: 1

Pull-up resistors: 117

Open-drain outputs: 117

5-V tolerance: 53

 100-pin TFLGA (in planning), 100-pin LQFP

I/O pins: 78

Input pin: 1

Pull-up resistors: 78

Open-drain outputs: 78

5-V tolerance: 44

 80-pin LQFP

I/O pins: 58

Input pin: 1

Pull-up resistors: 58

Open-drain outputs: 58

5-V tolerance: 34

Table 1.1

Outline of Specifications (2/5)

Classification

Module/Function

Description

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