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R5F5630ACDFB bảng dữ liệu(PDF) 136 Page - Renesas Technology Corp

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R01DS0060EJ0100 Rev.1.00
Page 136 of 168
Sep 13, 2011
RX630 Group
5. Electrical Characteristics
5.4.5
Timing of On-Chip Peripheral Modules
Note 1. tPcyc: PCLK cycle
Table 5.15
Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
Ta = Topr
High drive output is selected by the drive capacity control register.
Item
Symbol
Min.
Max.
Unit*1
Test
Conditions
I/O ports
Input data pulse width
tPRW
1.5
—
tPcyc
Figure 5.24
MTU
Input capture input pulse
width
Single-edge
setting
tTICW
1.5
—
tPcyc
Figure 5.25
Both-edge
setting
2.5
—
Timer clock pulse width
Single-edge
setting
tTCKWH,
tTCKWL
1.5
—
tPcyc
Figure 5.26
Both-edge
setting
2.5
—
Phase counting
mode
2.5
—
POE
POE# input pulse width
tPOEW
1.5
—
tPcyc
Figure 5.27
8-bit timer
Timer clock pulse width
Single-edge
setting
tTMCWH,
tTMCWL
1.5
—
tPcyc
Figure 5.28
Both-edge
setting
2.5
—
SCI
Input clock cycle
Asynchronous
tScyc
4—
tPcyc
Figure 5.29
Clock
synchronous
6—
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—20
ns
Input clock fall time
tSCKf
—20
ns
Output clock cycle
Asynchronous
tScyc
16
—
tPcyc
Clock
synchronous
4—
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—20
ns
Output clock fall time
tSCKf
—20
ns
Transmit data delay time
Clock
synchronous
tTXD
—
40
ns
Figure 5.30
Receive data setup time
Clock
synchronous
tRXS
40
—
ns
Receive data hold time
Clock
synchronous
tRXH
40
—
ns
A/D
converter
10-bit A/D converter trigger input pulse width
tTRGW
1.5
—
tPcyc
Figure 5.31
12-bit A/D converter trigger input pulse width
1.5
—



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