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R5F5630ACDFB bảng dữ liệu(PDF) 116 Page - Renesas Technology Corp |
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R5F5630ACDFB bảng dữ liệu(HTML) 116 Page - Renesas Technology Corp |
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116 / 165 page ![]() R01DS0060EJ0100 Rev.1.00 Page 116 of 168 Sep 13, 2011 RX630 Group 4. I/O Registers Note 2. When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address is 000881EDh. When different output triggers are specified, the PPG0.NDRL addresses for pulse output groups 0 and 1 are 000881EFh and 000881EDh, respectively. Note 3. When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address is 000881FCh. When different output triggers are specified, the PPG1.NDRH addresses for pulse output groups 6 and 7 are 000881FEh and 000881FCh, respectively. Note 4. When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address is 000881FDh. When different output triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 000881FFh and 000881FDh, respectively. Note 5. Odd addresses should not be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMR0 or TMR2 register. Table 25.4 lists register allocation for 16-bit access. Note 6. The CAN2 module is not provided in products less than 1 Mbyte of ROM. Note 7. The CAN0 module is not provided in products less than 512 Kbytes of ROM. Note 8. When the register is accessed while the USB is operating, a delay may be generated in accessing. |
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