R5F64110DFB datasheet(10/108 Pages) RENESAS

10 / 108 page

R01DS0062EJ0120 Rev.1.20

Page 10 of 99

Sep 26, 2011

R32C/111 Group

1. Overview

1.3

Block Diagram

Figure 1.2 to Figure 1.4 show block diagram of the R32C/111 Group.

Figure 1.2

R32C/111 Group Block Diagram for the 100-pin Package

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

VCC2

VCC1

X-Y converter:

16 bits × 16 bits

CRC calculator (CCITT)

X16 + X12 + X5 + 1

Watchdog timer:

15 bits

R32C/100 Series CPU Core

R2R0

R3R1

R6R4

R7R5

FLG

INTB

ISP

USP

SVF

SVP

VCT

Memory

ROM

RAM

Multiplier

Floating-point unit

R2R0

R3R1

R6R4

R7R5

D/A converter:

8 bits × 2 channels

A/D converter:

10 bits × 1 circuit

Standard: 10 inputs

Maximum: 26 inputs

Timer:

Timer A 16 bits × 5 timers

Timer B 16 bits × 6 timers

Three-phase motor

controller

Serial interface:

9 channels

Intelligent I/O

Time measurement: 16

Wave generation: 19

Serial interface:

- Variable-length

synchronous serial I/O

- IEBus

Clock generator:

4 circuits

- XIN-XOUT

- XCIN-XCOUT

- On-chip oscillator

- PLL frequency synthesizer

DMAC

DMAC II

Peripheral functions

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