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HT45F43 bảng dữ liệu(PDF) 105 Page - Holtek Semiconductor Inc |
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HT45F43 bảng dữ liệu(HTML) 105 Page - Holtek Semiconductor Inc |
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105 / 152 page ![]() OPA1 I/O status description: The following table illustrates the OPA1 I/O settings. A1EN A1NS A1PS IO2(A1N), IO3(A1P), IO4(A1E) 0 x x IO2, IO3, IO4 are I/Os 1 0 0 IO2, IO3 are I/Os. A1E is OPA1 output 1 0 1 IO2 is I/O. A1P is OPA1 input, A1E is OPA1 output 1 1 0 IO3 is I/O. A1N is OPA1 input, A1E is OPA1 output 1 1 1 A1N, A1P are OPA1 inputs, A1E is OPA1 output OPA2 Switch Control The following diagram and table illustrate the OPA2 switch control setting and the corresponding connections. Note that some switch control selections will force some switches to be controlled by hardware automatically. For example: · The PGAEN=1 will force S6D, S7D to close and the PGAEN=0 will force S6D, S7D to open. · When the A2EN=0, these switches, S6D, S7D and S9D, are opened by hardware, then the related I/O pins can be used as the other functions. Note: S1D, S2D and S3D are for HT45F23 only. Switch priority: S4D > S11D > (S12D, S13D, S14D); if A2PS=1, S11D~S14D will be opened by hardware. Switch Priority: S5D > S8D; if A2NS=1, S8D will be opened by hardware. HT45F23/HT45F43 8-Bit Flash MCU with Op Amps & Comparators Rev. 1.20 105 September 15, 2011 |
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