HT45F43 datasheet(94/152 Pages) HOLTEK

94 / 152 page

Rev. 1.20

September 15, 2011

HT45F23/HT45F43

8-Bit Flash MCU with Op Amps & Comparators

D a t a

S = S t a r t ( 1 b i t )

S A = S l a v e A d d r e s s ( 7 b i t s )

S R = S R W b i t ( 1 b i t )

M = S l a v e d e v i c e s e n d a c k n o w l e d g e b i t ( 1 b i t )

D = D a t a ( 8 b i t s )

A = A C K ( R X A K b i t f o r t r a n s m i t t e r , T X A K b i t f o r r e c e i v e r 1 b i t )

P = S t o p ( 1 b i t )

S C L

S t a r t

S D A

S R W

A C K

S t o p

S C L

S D A

S l a v e A d d r e s s

S A

S R

S A

S R

Note:

* When a slave address is matched, the device must be placed in either the transmit mode and then write data

to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to

release the SCL line.

2C Communication Timing Diagram

S t a r t

H A A S = 1

H T X = 1

S R W = 1

Y e s

N o

Y e s

N o

R X A K = 1

Y e s

N o

R e a d f r o m

S I M D t o r e l e a s e

S C L l i n e

R E T I

Y e s

D u m m y r e a d f r o m

S I M D t o r e l e a s e

S C L L i n e

R E T I

W r i t e d a t a t o S I M D

r e l e a s e S C L L i n e

S E T H T X

W r i t e d a t a t o S I M D

t o r e l e a s e S C L L i n e

R E T I

C L R H T X

C L R T X A K

D u m m y r e a d f r o m

S I M D t o r e l e a s e

S C L L i n e

C L R H T X

C L R T X A K

R E T I

2C Bus ISR Flow Chart

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