HT45F43 datasheet(60/152 Pages) HOLTEK

60 / 152 page

Programming Considerations

Within the user program, one of the first things to consider is port initialisation. After a reset, all of the

I/O data and port control registers will be set high. This means that all I/O pins will default to an input

state, the level of which depends on the other connected circuitry and whether pull-high selections

have been chosen. If the port control registers, PAC~PCC, are then programmed to setup some pins as

outputs, these output pins will have an initial high output value unless the associated port data

registers, PA~PC, are first programmed. Selecting which pins are inputs and which are outputs can be

achieved byte-wide by loading the correct values into the appropriate port control register or by

programming individual bits in the port control register using the

²SET[m].i² and ²CLR[m].i²

instructions. Note that when using these bit control instructions, a read-modify-write operation takes

place. The microcontroller must first read in the data on the entire port, modify it to the required new

bit values and then rewrite this data back to the output ports.

Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP

or IDLE Mode, various methods are available to wake the device up. One of these is a high to low

transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.

In addition, the Port B pins also provide Open Drain I/O structure options which can be controlled by

the specific register.

Rev. 1.20

September 15, 2011

HT45F23/HT45F43

8-Bit Flash MCU with Op Amps & Comparators

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

W r i t e t o P o r t

R e a d f r o m P o r t

S y s t e m C l o c k

P o r t D a t a

Read Modify Write Timing

V D D

B Z E N , P F D E N ,

P F W M E N

C o n t r o l B i t

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

C K

P A 0 ~ P A 7

P B 0 ~ P B 6

P C 0 ~ P C 6

I N T 0 f o r P A 3 o n l y

I N T 1 f o r P B 0 o n l y

T C 0 f o r P A 1 o n l y

T C 1 f o r P A 4 o n l y

S y s t e m W a k e - u p ( P A 0 ~ P A 7 )

R e a d D a t a R e g i s t e r

P A 7 / P A 6 / P A 5 / P C 5 / P C 6

B Z / B Z / P F D / P W M 0 / P W M 1

W a k e - u p R e g i s t e r

P u l l - H i g h

O p t i o n

P B 0 ~ P B 3 O p e n D r a i n O p t i o n

Generic Input/Output Ports

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