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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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MCD212 bảng dữ liệu(PDF) 21 Page - Motorola, Inc |
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MCD212 bảng dữ liệu(HTML) 21 Page - Motorola, Inc |
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21 / 87 page  MCD212 3–2 MOTOROLA The result of a reset will be a constant black level at the RGB outputs and no video synchronization output. The active low reset pin must be connected to the system reset signal. The RSTIN also has an effect on the clock output CLK2 (see Figure 3–2). Two different waveforms for CLK2 are possible. It can be seen that CLK2 is present during and after reset. CLK RSTIN CLK2 OR CLK2 Figure 3–2. CLK2 Clocking and Resetting CLK2 is clocked by the positive edge of CLK. Its phase after reset is related to the rising edge of RSTIN. CLK2 is always the inverse of CLK2. 3.3 VDSC INITIALIZATION SEQUENCE In order to have a proper start–up, register CSR1W must be initialized to the DRAM used. Display and control data must be loaded in DRAM. Register DCR1 must be initialized to the required display mode at a rising edge of the DA–bit (CSR1R register). At a falling edge of the DA–bit (CSR1R register), the DE–bit (DCR1 register) must be set. Now video synchronization is generated. On the next rising edge of the DA–bit, the IC1 bit (DCR1 register) and IC2–bit (DCR2 register) must be set and on the next falling edge of the DA–bit the DC1–bit (DCR1 register) and DC2–bit (DCR2 register) must be set. Now the RGB outputs will generate a picture. 3.4 MEMORY SWAPPING After RSTIN is released the first four 680X0 word accesses are counted. If CS is asserted at such a word access, a chip select to the ROM is given. The 680X0 first four accesses correspond to the SSP (System Stack Pointer) and the PC (Program Counter). The SSP and PC must be located at address h400000 and h400004 which are decoded during the swapping. Address h0 to h7 are normally decoded afterwards. RTSIN U/LDS ADDRESS ACCESS TYPE h0 h2 h4 h6 PC ROM ROM ROM ROM ROM OR RAM ROM Figure 3–3. Memory Swapping Timing Chart |
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