MCD212 datasheet(69/87 Pages) MOTOROLA

tên linh kiện	MCD212

Giải thích chi tiết về linh kiện	Video Decoder and System Controller(with JTAG)

PDF	87 Pages

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nhà sản xuất	MOTOROLA [Motorola, Inc]

Trang chủ	http://www.freescale.com

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69 / 87 page

MCD212

9–6

MOTOROLA

9.1.4

Display Decoder Registers DDR1 and DDR2

These registers contain control bits for the display, files to be displayed, and the six MSB bits of the

DCA pointer. All the bits, except the six LSBs, are reset to 0 after the reset sequence.

DDR1 (write, 4FFFF8)

Table 9–16. Display Decoder Register 1 — Write, 4FFFF8

—

MF1

MF2

FT1

FT2

—

A21

A20

A19

A18

A17

A16

MF1 – MF2

(Mosaic Factor) Set the horizontal mosaic factor:

Table 9–17. Channel 1 Mosiac Factor

MF1

MF2

Mosaic Factor

FT1 – FT2

(File type) Indicate the type of file to be displayed:

Table 9–18. Channel 1 Display File Type

FT1

FT2

Display File Type

Bitmap

Run–length

Mosaic

A21 – A16

Most significant bits of the DCA1 pointer.

DDR2 (write,4FFFE8)

Table 9–19. Display Decoder Register 2 — Write, 4FFFE8

—

MF1

MF2

FT1

FT2

—

A21

A20

A19

A18

A17

A16

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