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STTS2002 bảng dữ liệu(PDF) 36 Page - STMicroelectronics |
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STTS2002 bảng dữ liệu(HTML) 36 Page - STMicroelectronics |
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36 / 52 page ![]() SPD EEPROM operation STTS2002 36/52 Doc ID 15389 Rev 5 5.6 Read operations - SPD Read operations are performed independently of whether hardware or software protection has been set. The device has an internal address counter which is incremented each time a byte is read. Figure 14. Read mode sequences - SPD 1. The seven most significant bits of the device select code of a random read (in the 1st and 3rd bytes) must be identical. 5.6.1 Random address read - SPD A dummy write is first performed to load the address into this address counter (as shown in Figure 14) but without sending a stop condition. Then, the bus master sends another start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a stop condition. DEV SEL (1) BYTE ADDR DEV SEL DATA OUT 1 AI01942 DATA OUT N CURRENT ADDRESS READ DEV SEL DATA OUT RANDOM ADDRESS READ DEV SEL (1) DATA OUT SEQUENTIAL CURRENT READ DATA OUT N DEV SEL (1) BYTE ADDR SEQUENTIAL RANDOM READ DEV SEL (1) DATA OUT 1 ACK R/W NO ACK ACK R/W ACK ACK R/W ACK ACK ACK NO ACK R/W NO ACK ACK ACK R/W ACK ACK R/W ACK NO ACK |
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