SAM3U datasheet(41/59 Pages) ATMEL

41 / 59 page

6430ES–ATARM–22-Aug-11

SAM3U Series

10.13 Chip Identification

• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.

• JTAG ID: 0x0582A03F

10.14 PIO Controllers

• 3 PIO Controllers, PIOA, PIOB, and PIOC, controlling a maximum of 96 I/O Lines

• Each PIO Controller controls up to 32 programmable I/O Lines

– PIOA has 32 I/O Lines

– PIOB has 32 I/O Lines

– PIOC has 32 I/O Lines

• Fully programmable through Set/Clear Registers

• Multiplexing of two peripheral functions per I/O Line

• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)

– Input change, rising edge, falling edge, low level and level interrupt

– Debouncing and Glitch filter

– Multi-drive option enables driving in open drain

– Programmable pull up on each I/O line

– Pin data status register, supplies visibility of the level on the pin at any time

• Synchronous output, provides Set and Clear of several I/O lines in a single write

Table 10-1.

SAM3U Chip IDs Register - Engineering Samples

Chip Name

Flash Size

KByte

Pin Count

CHIPID_CIDR

CHIPID_EXID

SAM3U4C

256

100

0x28000960

0x0

SAM3U2C

128

100

0x280A0760

0x0

SAM3U1C

100

0x28090560

0x0

SAM3U4E

256

144

0x28100960

0x0

SAM3U2E

128

144

0x281A0760

0x0

SAM3U1E

144

0x28190560

0x0

Table 10-2.

SAM3U Chip IDs Register - Revision A Parts

Chip Name

Flash Size

KByte

Pin Count

CHIPID_CIDR

CHIPID_EXID

SAM3U4C (Rev A)

256

100

0x28000961

0x0

SAM3U2C (Rev A)

128

100

0x280A0761

0x0

SAM3U1C (Rev A)

100

0x28090561

0x0

SAM3U4E (Rev A)

256

144

0x28100961

0x0

SAM3U2E (Rev A)

128

144

0x281A0761

0x0

SAM3U1E (Rev A)

144

0x28190561

0x0

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