SAM3U datasheet(28/59 Pages) ATMEL

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6430ES–ATARM–22-Aug-11

SAM3U Series

7.6

DMA Controller

• Acting as one Matrix Master

• Embeds 4 channels:

– 3 channels with 8 bytes/FIFO for Channel Buffering

– 1 channel with 32 bytes/FIFO for Channel Buffering

• Linked List support with Status Write Back operation at End of Transfer

• Word, HalfWord, Byte transfer support.

• Handles high speed transfer of SPI, SSC and HSMCI (peripheral to memory, memory to

peripheral)

• Memory to memory transfer

• Can be triggered by PWM and T/C which enables to generate waveforms though the

External Bus Interface

The DMA controller can handle the transfer between peripherals and memory and so receives

the triggers from the peripherals listed below. The hardware interface numbers are also given in

Table 7-4 below.

7.7

Peripheral DMA Controller

•

Handles data transfer between peripherals and memories

•

Nineteen channels

–

Two for each USART

–

Two for the UART

–

Two for each Two Wire Interface

–

One for the PWM

–

One for each Analog-to-digital Converter

•

Low bus arbitration overhead

– One Master Clock cycle needed for a transfer from memory to peripheral

– Two Master Clock cycles needed for a transfer from peripheral to memory

•

Next Pointer management for reducing interrupt latency requirement

Table 7-4.

DMA Controller

Instance name

Channel T/R

DMA Channel HW interface

Number

HSMCI

Transmit/Receive

SPI

Transmit

SPI

Receive

SSC

Transmit

SSC

Receive

PWM Event Line 0

Trigger

PWM Event Line 1

Trigger

TIO Output of TImer

Counter Channel 0

Trigger

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