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LSM330DLTR bảng dữ liệu(PDF) 15 Page - STMicroelectronics

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LSM330DL
Module specifications
Doc ID 022018 Rev 1
15/54
2.4.2
I2C - inter-IC control interface
The values given in the following table are subject to the general operating conditions for
Vdd and TOP.
Figure 4.
I2C slave timing diagram (3)
1.
Data based on standard I2C protocol requirement, not tested in production.
2
Cb = total capacitance of one bus line, in pF
3.
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
Table 7.
I2C slave timing values
Symbol
Parameter(1)
I2C standard mode
I2C fast mode (1)
Unit
Min
Max
Min
Max
f(SCL)
SCL clock frequency
0
100
0
400
kHz
tw(SCLL)
SCL clock low time
4.7
1.3
µs
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
ns
th(SDA)
SDA data hold time
0.01
3.45
0
0.9
µs
tr(SDA) tr(SCL) SDA and SCL rise time
1000
20 + 0.1Cb
(2)
300
ns
tf(SDA) tf(SCL) SDA and SCL fall time
300
20 + 0.1Cb
(2)
300
th(ST)
START condition hold time
4
0.6
µs
tsu(SR)
Repeated START condition setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
tw(SP:SR)
Bus free time between STOP and
START condition
4.7
1.3
1.
SCL (SCL_A/G pin), SDA (SDA_A/G pin)
SDA
SCL
tf(SDA)
tsu(SP)
tw(SCLL)
tsu(SDA)
tr(SDA)
tsu(SR)
th(ST)
tw(SCLH)
th(SDA)
tr(SCL)
tf(SCL)
tw(SP:SR)
START
REPEATED
START
STOP
START
AM09238V1



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