LIS35DETR datasheet(18/39 Pages) STMICROELECTRONICS

18 / 39 page

Digital interfaces

LIS35DE

18/39

Doc ID 15594 Rev 1

5.1.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the Master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the Master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the Master.

The Slave ADdress (SAD) associated to the LIS35DE is 001110xb. SDO pad can be used to

modify less significant bit of the device address. If SDO pad is connected to voltage supply

LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’

(address 0011100b). This solution permits to connect and address two different

accelerometer to the same I2C lines.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data has

been received.

The I2C embedded inside the LIS35DE behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a salve address is sent, once a

slave acknowledge (SAK) has been returned, a 8-bit sub-address is transmitted: the 7 LSb

represent the actual register address while the MSB enables address auto increment. If the

MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow

multiple data read/write.

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)

the Master will transmits to the slave with direction unchanged.

Table 10 explains how the

SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Table 10.

SAD+Read/Write patterns

Command

SAD[6:1]

SAD[0] = SDO

R/W

SAD+R/W

Read

001110

00111001 (39h)

Write

001110

00111000 (38h)

Read

001110

00111011 (3Bh)

Write

001110

00111010 (3Ah)

Table 11.

Transfer when Master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

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