W25Q16CLZPIP datasheet(2/77 Pages) WINBOND

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W25Q16CL

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Table of Contents

GENERAL DESCRIPTION ............................................................................................................... 5

FEATURES....................................................................................................................................... 5

PIN CONFIGURATION SOIC 150 / 208-MIL ................................................................................... 6

PAD CONFIGURATION WSON 6X5-MM ........................................................................................ 6

PIN CONFIGURATION PDIP 300-MIL............................................................................................. 7

PIN DESCRIPTION SOIC 150/208-MIL, PDIP 300-MIL AND WSON 6X5-MM............................... 7

PIN CONFIGURATION SOIC 300-MIL ............................................................................................ 8

PIN DESCRIPTION SOIC 300-MIL .................................................................................................. 8

8.1

Package Types..................................................................................................................... 9

8.2

Chip Select (/CS).................................................................................................................. 9

8.3

Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................... 9

8.4

Write Protect (/WP)............................................................................................................... 9

8.5

HOLD (/HOLD) ..................................................................................................................... 9

8.6

Serial Clock (CLK)................................................................................................................ 9

BLOCK DIAGRAM.......................................................................................................................... 10

10.

FUNCTIONAL DESCRIPTION ....................................................................................................... 11

10.1

SPI OPERATIONS ............................................................................................................. 11

10.1.1

Standard SPI Instructions...................................................................................................11

10.1.2

Dual SPI Instructions ..........................................................................................................11

10.1.3

Quad SPI Instructions.........................................................................................................11

10.1.4

Hold Function .....................................................................................................................11

10.2

WRITE PROTECTION ....................................................................................................... 12

10.2.1

Write Protect Features........................................................................................................12

11.

CONTROL AND STATUS REGISTERS ........................................................................................ 13

11.1

STATUS REGISTER .......................................................................................................... 13

11.1.1

BUSY..................................................................................................................................13

11.1.2

Write Enable Latch (WEL) ..................................................................................................13

11.1.3

Block Protect Bits (BP2, BP1, BP0)....................................................................................13

11.1.4

Top/Bottom Block Protect (TB)...........................................................................................13

11.1.5

Sector/Block Protect (SEC) ................................................................................................13

11.1.6

Complement Protect (CMP) ...............................................................................................14

11.1.7

Status Register Protect (SRP1, SRP0)...............................................................................14

11.1.8

Erase/Program Suspend Status (SUS) ..............................................................................14

11.1.9

Security Register Lock Bits (LB3, LB2, LB1) ......................................................................14

11.1.10

Quad Enable (QE) ............................................................................................................15

11.1.11

Status Register Memory Protection (CMP = 0).................................................................16

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