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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HT16L21 bảng dữ liệu(PDF) 9 Page - Holtek Semiconductor Inc |
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HT16L21 bảng dữ liệu(HTML) 9 Page - Holtek Semiconductor Inc |
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9 / 36 page  Rev. 1.00 9 November 16, 2011 HT16L21 A.C. Characteristics – I2C Interface Unless otherwise specified, VSS=0V; VDD=1.8V to 5.5V; Ta=-40~85°C Symbol Parameter Condition VDD=1.8V to 5.5V VDD=3.0V to 5.5V Unit Min. Max. Min. Max. fSCL Clock Frequency — — 100 — 400 kHz tBUF Bus Free Time Time in which the bus must be free before a new transmission can start 4.7 — 1.3 — μs tHD: STA Start Condition Hold Time After this period, the first clock pulse is generated 4 — 0.6 — μs tLOW SCL Low Time — 4.7 — 1.3 — μs tHIGH SCL High Time — 4 — 0.6 — μs tSU: STA Start Condition Setup Time Only relevant for repeated START condition 4.7 — 0.6 — μs tHD: DAT Data Hold Time — 0 — 0 — ns tSU: DAT Data Setup Time — 250 — 100 — ns tR SDA and SCL Rise Time Note — 1 — 0.3 μs tF SDA and SCL Fall Time Note — 0.3 — 0.3 μs tSU: STO Stop Condition Set-Up Time — 4 — 0.6 — μs tAA Output Valid from Clock — — 3.5 — 0.9 μs tSP Input Filter Time Constant (SDA and SCL pins) Noise suppression time — 20 — 20 ns Note:Theseparametersareperiodicallysampledbutnot100%tested. A.C. Characteristics – SPI Interface Unless otherwise specified, VSS=0V; VDD=1.8V to 5.5V; Ta=-40~85°C Symbol Parameter Test Condition Min. Typ. Max. Unit VDD Condition tSYS Clock Cycle Time — For write data 250 — — ns For read data 1000 — — ns tCW Clock Pulse Width — For write data 50 — — ns — For read data 400 — — ns tDS Data Setup Time — For write data 50 — — ns tDH Data Hold Time — For write data 50 — — ns tCSW “H” CSB Pulse Width — — 50 — — ns tCSL CSB Setup Time (CSB↓―CLK↑) — For write data 50 — — ns For read data 400 — — ns tCSH CS Hold Time (CLK↑―CSB↑) — — 2 — — μs tPD DATA Output Delay Time (CLK―DIO) — CO=15pF tPD=10% to 90% — — 350 ns tPD=90% to 10% |
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