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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TJ2995DP bảng dữ liệu(PDF) 9 Page - HTC Korea TAEJIN Technology Co. |
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TJ2995DP bảng dữ liệu(HTML) 9 Page - HTC Korea TAEJIN Technology Co. |
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9 / 9 page  DDR Termination Regulator TJ2995 Oct. 2009 - Rev. 1.1 9/9 HTC PCB LAYOUT CONSIDERATIONS 1. AVIN and PVIN should be tied together for optimal performance. A local bypass capacitor should be placed as close as possible to the PVIN pin. 2. GND should be connected to a ground plane with multiple vias for improved thermal performance. 3. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For motherboard applications an ideal location would be at the center of the termination bus. 4. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference voltage. 5. VREF should be bypassed with a 0.01 μF or 0.1 μF ceramic capacitor for improved performance. This capacitor should be located as close as possible to the VREF pin. |
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