DS89C430 datasheet(39/46 Pages) DALLAS

39 / 46 page

DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers

39 of 46

Figure 14. System Clock Sources

4X/

CTM

CRYSTAL

OSCILLATOR

DIVIDE 1024

RING

OSCILLATOR

CLOCK

MULTIPLIER

CD0

CD1

SELECTOR

RING

ENABLE

MUX

SYSTEM

CLOCK

Bandgap-Monitored Interrupt and Reset Generation

The power monitor in the DS89C430 monitors the VCC pin in relation to the on-chip bandgap voltage reference.

Whenever VCC falls below VPFW, an interrupt is generated if the corresponding power-fail interrupt-enable bit EPFI

(WDCON.5) is set, causing the device to vector to address 33h. The power-fail interrupt status bit PFI (WDCON.4)

is set any time VCC transitions below VPFW, and can only be cleared by software once set. Similarly, as VCC falls

below VRST, a reset is issued internally to halt program execution. Following power-up, a power-on reset initiates a

power-on reset timeout before starting program execution. When VCC is first applied to the DS89C430, the

processor is held in reset until VCC > VRST and a delay of 65,536 oscillator cycles has elapsed, to ensure that power

is within tolerance and the clock source has had time to stabilize. Once the reset timeout period has elapsed, the

reset condition is removed automatically and software execution begins at the reset vector location of 0000h. The

power-on reset flag POR (WDCON.6) is set to logic 1 to indicate a power-on reset has occurred, and can only be

cleared by software.

When the DS89C430 enters stop mode, the bandgap, reset comparator, and power-fail interrupt comparator are

automatically disabled to conserve power if the BGS (EXIF.0) bit is set to logic 0. This is the lowest power mode. If

BGS is set to logic 1, the bandgap reference, reset comparator, and the power-fail comparator are powered up,

although in a mode that reduces their power consumption.

DS89C430 bảng dữ liệu(PDF) 39 Page - Dallas Semiconductor