DS89C430 datasheet(15/46 Pages) DALLAS

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DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers

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Terminology

The term DS89C430 is used in the remainder of the document to refer to the DS89C430 and DS89C450, unless

otherwise specified.

Compatibility

The DS89C430 is a fully static CMOS 8051-compatible microcontroller similar in functional features to the

DS87C520, but it offers much higher performance. In most cases, the DS89C430 can drop into an existing socket

for the 8xC51 family, immediately improving the operation. While remaining familiar to 8051 family users, the

DS89C430 has many new features. In general, software written for existing 8051-based systems works without

modification on the DS89C430, with the exception of critical timing routines, as the DS89C430 performs its

instructions much faster for any given crystal selection.

The DS89C430 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes of direct RAM plus

1kB of extra MOVX RAM. I/O ports can operate as in standard 8051 products. Timers default to 12 clocks-per-

cycle operation to keep their timing compatible with a legacy 8051 family systems. However, timers are individually

programmable to run at the new one clock per cycle if desired. The DS89C430 provides several new hardware

features, described in subsequent sections, implemented by new special-function registers (SFRs).

Performance Overview

Featuring a completely redesigned high-speed 8051-compatible core, the DS89C430 allows operation at a higher

clock frequency. This updated core does not have the wasted memory cycles that are present in a standard 8051.

A conventional 8051 generates machine cycles using the clock frequency divided by 12. The same machine cycle

takes one clock in the DS89C430. Thus, the fastest instructions execute 12 times faster for the same crystal

frequency (and actually 24 times faster for the INC data pointer instruction). It should be noted that this speed

improvement is reduced when using external memory access modes that require more than one clock per cycle.

Individual program improvement depends on the instructions used. Speed-sensitive applications would make the

most use of instructions that are 12 times faster. However, the sheer number of 12-to-1 improved op codes makes

dramatic speed improvements likely for any code. These architectural improvements produce instruction cycle

times as low as 30ns. The dual data pointer feature also allows the user to eliminate wasted instructions when

moving blocks of memory. The new page modes allow for increased efficiency in external memory accesses.

Instruction Set Summary

All instructions have the same functionality as their 8051 counterparts, including their affect on bits, flags, and other

status functions. However, the timing of each instruction is different, in both absolute and relative number of clocks.

For absolute timing of real-time events, the duration of software loops can be calculated using information given in

the Instruction Set table in the Ultra-High-Speed Flash Microcontroller User’s Guide. However, counter/timers

default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals

with software executing at higher speed. Timers optionally can run at a reduced number of clocks per increment to

take advantage of faster processor operation.

The relative time of some instructions may be different in the new architecture. For example, in the original

architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction used two machine cycles

or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS89C430, the MOVX instruction

takes as little as two machine cycles or two oscillator cycles, but the “MOV direct, direct” uses three machine cycles

or three oscillator cycles. While both are faster than their original counterparts, they now have different execution

times. This is because the DS89C430 usually uses one machine cycle for each instruction byte and requires one

cycle for execution. The user concerned with precise program timing should examine the timing of each instruction

to become familiar with the changes.

Special-Function Registers (SFRs)

All peripherals and operations that are not explicit instructions in the DS89C430 are controlled through SFRs. The

most common features basic to the architecture are mapped to the SFRs. These include the CPU registers (ACC,

B, and PSW), data pointers, stack pointer, I/O ports, timer/counters, and serial ports. In many cases, an SFR

controls an individual function or reports the function’s status. The SFRs reside in register locations 80h–FFh and

are only accessible by direct addressing. SFRs with addresses ending in 0h or 8h are bit addressable.

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