MSP430F423IPM datasheet(21/45 Pages) TI

21 / 45 page

MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421A − APRIL 2004 − REVISED JUNE 2007

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

wake-up LPM3

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f = 1 MHz

td(LPM3)

Delay time

f = 2 MHz

VCC = 3 V

μs

td(LPM3)

Delay time

f = 3 MHz

VCC 3 V

μs

RAM (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VRAMh

CPU halted (see Note 1)

1.6

NOTE 1: This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program

execution should take place during this supply voltage condition.

LCD

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V(33)

Voltage at R33

2.5

VCC +0.2

V(23)

Analog voltage

Voltage at R23

(V33−V03) × 2/3 + V03

V(13)

Analog voltage

Voltage at R13

VCC = 3 V

(V(33)−V(03)) × 1/3 + V(03)

V(33) − V(03)

Voltage at R33/R03

2.5

VCC +0.2

I(R03)

R03 = VSS

No load at all

±20

I(R13)

Input leakage

R13 = VCC/3

segment and

common lines

±20

I(R23)

R23 = 2

× VCC/3

common lines,

VCC = 3 V

±20

V(Sxx0)

V(03)

V(03) − 0.1

V(Sxx1)

Segment line

3 A

V(13)

V(13) − 0.1

V(Sxx2)

Segment line

voltage

I(Sxx) = −3 μA,

VCC = 3 V

V(23)

V(23) − 0.1

V(Sxx3)

V(33)

V(33) + 0.1

USART0 (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

t(τ)

USART0: deglitch time

VCC = 3 V, SYNC = 0, UART mode

150

280

500

NOTE 1: The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the URXS

flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to

set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the

URXD0 line.

POR brownout, reset (see Notes 1 and 2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td(BOR)

2000

μs

VCC(start)

dVCC/dt ≤ 3 V/s (see Figure 6)

0.7

× V(B_IT−)

V(B_IT−)

Brownout

dVCC/dt ≤ 3 V/s (see Figure 6, Figure 7, and Figure 8)

1.71

Vhys(B_IT−)

Brownout

dVCC/dt ≤ 3 V/s (see Figure 6)

130

180

t(reset)

Pulse length needed at RST/NMI pin to accepted reset internally,

VCC = 3 V

μs

NOTES:

1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level

V(B_IT−) + Vhys(B_IT−) is ≤ 1.8 V.

2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−).

The default FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired

operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.

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