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PIC24F04KA201 bảng dữ liệu(PDF) 32 Page - Microchip Technology

tên linh kiện PIC24F04KA201
Giải thích chi tiết về linh kiện  Flash Programming Specifications
PDF  48 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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PIC24F04KA201 bảng dữ liệu(HTML) 32 Page - Microchip Technology

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PIC24FXXKAXXX
DS39919A-page 32
Advance Information
© 2008 Microchip Technology Inc.
5.0
THE PROGRAMMING
EXECUTIVE
This section describes the programming executive
communication, programming executive commands,
programming
responses,
programming
the
programming executive to memory and programming
verification.
5.1
Programming Executive
Communication
The programmer and the programming executive have
a master-slave relationship, where the programmer is
the master programming device and the programming
executive is the slave.
Communication is initiated by the programmer in the
form of a command. Only one command at a time can be
sent to the programming executive. The programming
executive, in turn, only sends one response to the
programmer after receiving and processing a command.
The programming executive command set is described
in
Section 5.2
“Programming
Executive
Commands”. The response set is described in
Section 5.3 “Programming Executive Responses”.
5.1.1
COMMUNICATION INTERFACE
AND PROTOCOL
The Enhanced ICSP interface is a two-wire SPI,
implemented using the PGCx and PGDx pins. The
PGCx pin is used as a clock input pin; the programmer
should provide the clock source. The PGDx pin is used
to send the command data to, and receive response
data from, the programming executive.
Data transmits to the device should change on the
rising edge and hold on the falling edge of PGCx.
Data receives from the device change on the falling
edge and holds on the rising edge of PGCx.
The data transmissions are sent to the MSB first using
16-bit mode (see Figure 5-1 and Figure 5-2).
FIGURE 5-1:
PROGRAMMING
EXECUTIVE SERIAL
TIMING FOR DATA
RECEIVED FROM DEVICE
As a 2-wire SPI is used and data transmissions are
half-duplex, a simple protocol is used to control the
direction of PGDx. When the programmer completes a
command transmission, it releases the PGDx line and
allows the programming executive to drive this line
high. The programming executive keeps the PGDx line
high to indicate that it is processing the command.
After the programming executive has processed the
command, it brings PGDx low for 15
μsec to indicate to
the programmer that the response is available to be
clocked out. The programmer can begin to clock out
the response 23
μsec after PGDx is brought low, and it
must provide the necessary amount of clock pulses to
receive the entire response from the programming
executive.
After
the
entire
response
is
clocked
out,
the
programmer should terminate the clock on PGCx until
it is time to send another command to the programming
executive; Figure 5.2 displays this protocol.
5.1.2
SPI RATE
In Enhanced ICSP mode, the PIC24FXXKAXXX family
devices operate from the internal Fast RC Oscillator,
which has a nominal frequency of 8 MHz. This
oscillator frequency yields an effective system clock
frequency of 4 MHz. To ensure that the programmer
does not clock too fast, it is recommended that a 4 MHz
clock be provided by the programmer.
FIGURE 5-2:
PROGRAMMING
EXECUTIVE SERIAL
TIMING FOR DATA
TRANSMITTED TO DEVICE
PGCx
PGDx
12
3
11
13
15
16
14
12
LSb
14
13
12
11
45
6
MSb
1
2
3
...
4
5
P2
P3
P1
P1B
P1A
PGCx
PGDx
12
3
11
13
15
16
14
12
LSb
14
13
12
11
45
6
MSb
1
2
3
...
4
5
P2
P3
P1
P1B
P1A



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