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PIC24F04KA201 bảng dữ liệu(PDF) 30 Page - Microchip Technology

tên linh kiện PIC24F04KA201
Giải thích chi tiết về linh kiện  Flash Programming Specifications
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nhà sản xuất  MICROCHIP [Microchip Technology]
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PIC24FXXKAXXX
DS39919A-page 30
Advance Information
© 2008 Microchip Technology Inc.
IESO
FOSCSEL<7>
Internal External Switchover bit
1
= Internal External Switchover mode enabled (Two-Speed Start-up enabled)
0
= Internal External Switchover mode disabled (Two-Speed Start-up
disabled)
I2C1SEL(1)
FPOR<4>
Alternate I2C1 Pin Mapping bit(1)
0
= Alternate location for SCL1/SDA1 pins
1
= Default location for SCL1/SDA1 pins
MCLRE(2)
FPOR<7>
MCLR Pin Enable bit(2)
1
= MCLR pin enabled; RA5 input pin disabled
0
= RA5 input pin enabled; MCLR disabled
OSCIOFNC
FOSC<2>
CLKO Enable Configuration bit
1
= CLKO output signal active on the OSCO pin; primary oscillator must be
disabled or configured for the External Clock mode (EC) for the CLKO to
be active (POSCMD<1:0> = 11 or 00)
0
= CLKO output disabled
POSCMD<1:0>
FOSC<1:0>
Primary Oscillator Configuration bits
11
= Primary oscillator disabled
10
= HS Oscillator mode selected (4 MHz-25 MHz)
01
= XT Oscillator mode selected (100 kHz-4 MHz)
00
= External Clock mode selected
POSCFREQ<1:0> FOSC<4:3>
Primary Oscillator Frequency Range Configuration bits
11
= Primary oscillator/external clock input frequency greater than 8 MHz
10
= Primary oscillator/external clock input frequency between 100 kHz and
8 MHz
01
= Primary oscillator/external clock input frequency less than 100 kHz
00
= Reserved, do not use
PWRTEN
FPOR<3>
Power-up Timer Enable bit
0
= PWRT disabled
1
= PWRT enabled
RTCCKSEL
FDS<5>
RTCC Reference Clock Select bit
1
= RTCC uses SOSC as reference clock
0
= RTCC uses LPRC as reference clock
SOSCSEL
FOSC<5>
Secondary Oscillator Select bit
1
= Secondary oscillator configured for high-power operation
0
= Secondary oscillator configured for low-power operation
WDTPRE
FWDT<4>
WDT Prescaler
1
= WDT prescaler ratio of 1:128
0
= WDT prescaler ratio of 1:32
WDTPOST<3:0>
FWDT<3:0>
Watchdog Timer Postscale Select bits
1111
= 1:32,768
1110
= 1:16,384
•
•
•
0001
= 1:2
0000
= 1:1
WINDIS
FWDT<6>
Windowed Watchdog Timer Disable bit
1
= Standard WDT selected; windowed WDT disabled
0
= Windowed WDT enabled
TABLE 4-2:
PIC24FXXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
Note 1:
Applies only to the 28-pin device.
2:
The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user
from accidentally locking out the device from low-voltage test entry.



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