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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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MCP3901 bảng dữ liệu(PDF) 6 Page - Microchip Technology |
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MCP3901 bảng dữ liệu(HTML) 6 Page - Microchip Technology |
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6 / 62 page  MCP3901 DS22192D-page 6 © 2011 Microchip Technology Inc. SERIAL INTERFACE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply: AVDD = 4.5 to 5.5V, DVDD = 2.7 to 5.5V, -40°C < TA < +85°C, CLOAD = 30 pF Parameters Sym Min Typ Max Units Conditions Serial Clock Frequency fSCK — — — — 20 10 MHz MHz 4.5 ≤ DV DD ≤ 5.5 2.7 ≤ DV DD < 5.5 CS Setup Time tCSS 25 50 — — — — ns ns 4.5 ≤ DV DD ≤ 5.5 2.7 ≤ DV DD ≤ 5.5 CS Hold Time tCSH 50 100 — — — — ns ns 4.5 ≤ DV DD ≤ 5.5 2.7 ≤ DV DD < 5.5 CS Disable Time tCSD 50 — — ns Data Setup Time tSU 5 10 — — — — ns ns 4.5 ≤ DV DD ≤ 5.5 2.7 ≤ DV DD < 5.5 Data Hold Time t HD 10 20 — — — — ns ns 4.5 ≤ DV DD ≤ 5.5 2.7 ≤ DV DD < 5.5 Serial Clock High Time t HI 20 50 — — — — ns ns 4.5 ≤ DV DD ≤ 5.5 2.7 ≤ DV DD < 5.5 Serial Clock Low Time t LO 20 50 — — — — ns ns 4.5 ≤ DV DD ≤ 5.5 2.7 ≤ DV DD < 5.5 Serial Clock Delay Time t CLD 50 — — ns Serial Clock Enable Time t CLE 50 — — ns Output Valid from SCK Low t DO — — 50 ns 2.7 ≤ DV DD < 5.5 Modulator Output Valid from AMCLK High t DOMDAT — — 1/2 * AMCLK s Output Hold Time t HO 0— — ns (Note 1) Output Disable Time t DIS — — — — 25 50 ns ns 4.5 ≤ DV DD ≤ 5.5 2.7 ≤ DV DD < 5.5 (Note 1) Reset Pulse Width (RESET)tMCLR 100 — — ns 2.7 ≤ DV DD < 5.5 Data Transfer Time to DR (data ready) tDODR — — 50 ns 2.7 ≤ DV DD < 5.5 Data Ready Pulse Low Time tDRP —1/DMCLK — µs 2.7 ≤ DV DD < 5.5 Schmitt Trigger High-Level Input Voltage VIH1 .7 DVDD —DVDD + 1 V Schmitt Trigger Low-Level Input Voltage VIL1 -0.3 — 0.2 DVDD V Hysteresis of Schmitt Trigger Inputs (all digital inputs) VHYS 300 — — mV Low-Level Output Voltage, SDO Pin VOL — — 0.4 V SDO pin only, IOL = +2.0 mA, VDD = 5.0V Low-level output voltage, DR and MDAT Pins VOL —— 0.4 V DR and MDAT pins only, IOL = +800 mA, VDD = 5.0V High-level output voltage, SDO pin VOH DVDD – 0.5 — — V SDO pin only, IOH = -2.0 mA, VDD = 5.0V High-level output voltage, DR and MDAT pins VOH DVDD – 0.5 — — V DR and MDAT pins only, IOH = -800 µA, VDD = 5.0V Input leakage current ILI —— ±1 µA CS = DVDD, VIN = DGND or DVDD Output leakage current ILO —— ±1 µA CS = DVDD, VOUT = DGND or DVDD Internal capacitance (all inputs and outputs) CINT —— 7 pF TA = 25°C, SCK = 1.0 MHz, DVDD = 5.0V (Note 1) Note 1: This parameter is periodically sampled and not 100% tested. |
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