HT82K70E-L datasheet(35/59 Pages) HOLTEK

35 / 59 page

HT82K70E-L/HT82K70A-L/HT82K76E-L

Rev. 1.20

February 1, 2011

After Power on, the contents of the SBDR register will be

in an unknown condition while the SBCR register will de-

fault to the condition below:

CKS M1 M0 SBEN MLS CSEN WCOL TRF

00000

Note that data written to the SBDR register will only be

written to the TXRX buffer, whereas data read from the

SBDR register will actual be read from the register.

SPI Bus Enable/Disable

To enable the SPI bus, SBEN should be set high, then

SCK, SDI, SDO and SCS lines should all be zero, then

wait for data to be written to the SBDR (TXRX buffer)

ten to the SBDR (TXRX buffer) register then transmis-

sion or reception will start automatically. When all the

data has been transferred the TRF bit should be set. For

the Slave Mode, when clock pulses are received on

SCK, data in the TXRX buffer will be shifted out or data

on SDI will be shifted in.

To Disable the SPI bus SCK, SDI, SDO, SCS should be

floating.

SPI Operation

All communication is carried out using the 4-line inter-

face for both Master or Slave Mode. The timing diagram

shows the basic operation of the bus.

The SBEN bit in the SBCR register controls the SCS line

of the SPI interface. Setting this bit high, will enable the

SPI interface by allowing the SCS line to be active,

which can then be used to control the SPI interface. If

the SBEN bit is low, the SCS line will be in a floating con-

dition and can therefore not be used for control of the

SPI interface. The SBEN bit in the SBCR register must

also be high which will place the SDI line in a floating

condition and the SDO line high. If in the Master Mode

the SCK line will be either high or low depending upon

the clock polarity configuration option. If in the Slave

Mode the SCK line will be in a floating condition. If SBEN

is low then the bus will be disabled and SCS, SDI, SDO

and SCK will all be in a floating condition.

S B C R R e g i s t e r

b 7

b 0

C K S

M 1

M 0 S B E N M L S C S E N W C O L T R F

T r a n s m i t t / R e c e i v e f l a g

0 : n o t c o m p l e t e

1 : t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e

W r i t e c o l l i s i o n b i t

0 : c o l l i s i o n f r e e

1 : c o l l i s i o n d e t e c t e d

S e l e c t i o n s i g n a l e n a b l e / d i s a b l e b i t

0 : S C S f l o a t i n g

1 : e n a b l e

M S B / L S B F i r s t B i t

0 : L S B s h i f t f i r s t

1 : M S B s h i f t f i r s t

S e r i a l b u s e n a b l e / d i s a b l e b i t

0 : d i s a b l e

1 : e n a b l e

M a s t e r / S l a v e / B a u d r a t e b i t s

m a s t e r , b a u d r a t e : f S P I

m a s t e r , b a u d r a t e : f S P I / 4

m a s t e r , b a u d r a t e : f S P I / 1 6

s l a v e m o d e

M 1

M 0

C l o c k s o u r c e s e l e c t b i t

0 : f S P I = f S Y S / 4

1 : f S P I = f S Y S

SPI Interface Control Register

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