DSPIC30F2010 datasheet(59/202 Pages) MICROCHIP

59 / 202 page

DS70118J-page 59

dsPIC30F2010

9.4

Timer Interrupt

The 16-bit timer has the ability to generate an interrupt

on period match. When the timer count matches the

period register, the T1IF bit is asserted and an interrupt

will be generated, if enabled. The T1IF bit must be

cleared in software. The timer interrupt flag T1IF is

located in the IFS0 control register in the Interrupt

Controller.

When the Gated Time Accumulation mode is enabled,

an interrupt will also be generated on the falling edge of

the gate signal (at the end of the accumulation cycle).

Enabling an interrupt is accomplished via the respec-

tive timer interrupt enable bit, T1IE. The timer interrupt

enable bit is located in the IEC0 control register in the

Interrupt Controller.

9.5

Real-Time Clock

Timer1, when operating in Real-Time Clock (RTC)

mode, provides time-of-day and event time stamping

capabilities. Key operational features of the RTC are:

• Operation from 32 kHz LP oscillator

• 8-bit prescaler

• Low power

• Real-Time Clock Interrupts

• These Operating modes are determined by

setting the appropriate bit(s) in the T1CON

Control register

FIGURE 9-2:

RECOMMENDED

COMPONENTS FOR

TIMER1 LP OSCILLATOR

RTC

9.5.1

RTC OSCILLATOR OPERATION

When the TON = 1, TCS = 1 and TGATE = 0, the timer

increments on the rising edge of the 32 kHz LP oscilla-

tor output signal, up to the value specified in the period

The TSYNC bit must be asserted to a logic ‘0’

(Asynchronous mode) for correct operation.

Enabling LPOSCEN (OSCCON<1>) will disable the

normal Timer and Counter modes, and enable a timer

carry-out wake-up event.

When the CPU enters Sleep mode, the RTC will con-

tinue to operate, provided the 32 kHz external crystal

oscillator is active and the control bits have not been

changed. The TSIDL bit should be cleared to ‘0’ in

order for RTC to continue operation in Idle mode.

9.5.2

RTC INTERRUPTS

When an interrupt event occurs, the respective inter-

rupt flag, T1IF, is asserted and an interrupt will be gen-

erated, if enabled. The T1IF bit must be cleared in

software. The respective Timer interrupt flag, T1IF, is

located in the IFS0 status register in the Interrupt

Controller.

Enabling an interrupt is accomplished via the respec-

tive timer interrupt enable bit, T1IE. The Timer interrupt

enable bit is located in the IEC0 control register in the

Interrupt Controller.

SOSCI

SOSCO

dsPIC30F2010

32.768 kHz

XTAL

C1 = C2 = 18 pF; R = 100K

DSPIC30F2010 bảng dữ liệu(PDF) 59 Page - Microchip Technology

DSPIC30F2010 bảng dữ liệu(HTML) 59 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL