PCIMX536AVV8B datasheet(149/180 Pages) FREESCALE

149 / 180 page

Electrical Characteristics

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

149

4.7.19.2

Parallel Interface (Normal ULPI) Timing

Electrical and timing specifications of Parallel Interface (Normal ULPI) for Host Port2 and Port3 are

presented in the subsequent sections.

Figure 101. USB Transmit/Receive Waveform in Parallel Mode

4.7.20

USB PHY Parameters

This section describes the USB-OTG PHY and the USB Host port PHY parameters.

4.7.20.1

USB PHY AC Parameters

Table 101 lists the AC timing parameters for USB PHY.

Table 99. Signal Definitions - Parallel Interface (Normal ULPI)

Name

Direction

Signal Description

USB_Clk

Interface clock. All interface signals are synchronous to Clock.

USB_Data[7:0]

I/O

Bi-directional data bus, driven low by the link during idle. Bus

ownership is determined by Dir.

USB_Dir

Direction. Control the direction of the Data bus.

USB_Stp

Out

Stop. The link asserts this signal for 1 clock cycle to stop the

data stream currently on the bus.

USB_Nxt

Next. The PHY asserts this signal to throttle the data.

Table 100. USB Timing Specification for Normal ULPI mode

Parameter

Min

Max

Unit

Conditions /

Reference Signal

US15

Setup Time(Dir&Nxt in, Data in)

—

6.0

10 pF

US16

Hold Time(Dir&Nxt in, Data in)

—

0.0

10 pF

US17

Output delay Time(Stp out, Data out

—

9.0

10 pF

USB_Stp

USB_Dir/Nxt

US17

US16

USB_Data

US15

US16

US15

US17

USB_Clk

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