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PCIMX536AVV8B bảng dữ liệu(PDF) 132 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  i.MX53xA Automotive and Infotainment Applications Processors
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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PCIMX536AVV8B bảng dữ liệu(HTML) 132 Page - Freescale Semiconductor, Inc

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i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
132
Freescale Semiconductor
Electrical Characteristics
NOTE
•
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
•
All timings are on Audiomux Pads when SSI is being used for data
transfer.
•
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
•
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
•
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
SS17
(Tx) CK high to STXD high/low
—
15.0
ns
SS18
(Tx) CK high to STXD high impedance
—
15.0
ns
SS19
STXD rise/fall time
—
6.0
ns
Synchronous Internal Clock Operation
SS42
SRXD setup before (Tx) CK falling
10.0
—
ns
SS43
SRXD hold after (Tx) CK falling
0.0
—
ns
SS52
Loading
—
25.0
pF
Table 82. SSI Transmitter Timing with Internal Clock (continued)
ID
Parameter
Min
Max
Unit



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