PCA9525 datasheet(8/22 Pages) NXP

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PCA9525

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Product data sheet

Rev. 1 — 25 February 2011

8 of 22

NXP Semiconductors

PCA9525

Simple 2-wire bus buffer

This means that as direction control is handed from one side of the buffer to the other, a

voltage ‘spike’ of about Vunlock volts will appear on the side that was the ‘input’ and

became the ‘output’.

Figure 9 shows clock and data being buffered through the PCA9525. Channel 3 shows

the SDA_IN port, with direction ‘hand over’ spike (upper left corner). The level of the

SDA_OUT port (channel 4) can be seen to increase as it goes from being held LOW by

the buffer, to being held LOW by another device on the bus.

Of course, the information on the SDA line is only latched into an I2C-bus device on a

clock edge. The spike on the data line does not occur at a time when data is being

latched, and thus the set-up and hold conditions are still met for a valid I2C-bus

transaction.

Figure 9 also shows a glitch occurring on the SDA_OUT port (upper right corner). A more

drastic example is shown in Figure 10. In this case, the side acting as the ‘input’

(SDA_OUT) is more lightly loaded than the side acting as the ‘output’ (SDA_IN). It

therefore rises quickly to Vunlock level, before the SDA_IN has been able to exceed VIL.

Direction control briefly reverses, and SDA_OUT gets pulled back LOW again until

SDA_IN has exceeded VIH.

Fig 9.

‘Hand over’ spikes on the data bus

Fig 10. Fast rising SDA_xx ‘input’ side

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