F75125 datasheet(28/34 Pages) FINTEK

tên linh kiện	F75125

Giải thích chi tiết về linh kiện	Serial VID, Parallel VID Translator for AMD AM2 and AM2

PDF	34 Pages

Scroll/Zoom	100%

nhà sản xuất	FINTEK [Feature Integration Technology Inc.]

Trang chủ	http://www.fintek.com.tw/eng

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Fintek

Feature Integration Technology Inc.

V0.16P

F75125

7.13 VDDNB SVI Output Reading Register (LSB)

⎯ Index 0Ch

Bit

Name

R/W Default

Description

7-0

NB _OUT

SVID_OUT_NB (CR00+CR04)

7.14 VDD0 SVI Output Reading Register (LSB)

⎯ Index 0Dh

Bit

Name

R/W Default

Description

7-0

VDD0_OUT

SVID_OUT_VDD0 (CR01+CR05)

7.15 VDD1 SVI Output Reading Register (LSB)

⎯ Index 0Eh

Bit

Name

R/W Default

Description

7-0

VDD1_OUT

SVID_OUT_VDD1(CR02+CR06)

7.16 SLOTOCC Control Enable Reading Register

⎯ Index 0Fh

Bit

Name

R/W Default

Description

Reserved

6-1

DUMMY_REG

R/W

Dummy registers.

SLOTOCC_CLR_EN R/W

Enable SLOTOCC# pin to clear register

7.17 VDD_NB Voltage Value Register

⎯ Index 10h

Bit

Name

R/W Default

Description

7-0

VDDNB

This register can read VID value that input from SVI interface. This register

presents all the SVID code including bit 7, PSI_L.

7.18 VDD0 Voltage Value Register

⎯ Index 11h

Bit

Name

R/W Default

Description

7-0

VDD0

This register can read VID value that input from PVI/SVI interface. In PVI

input mode, MSB and LSB will be inserted “0” to complement 8 bit register.

For example, PVID code “111_111” will be read as 0x7E. In SVI mode, this

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