F75125 datasheet(9/34 Pages) FINTEK

tên linh kiện	F75125

Giải thích chi tiết về linh kiện	Serial VID, Parallel VID Translator for AMD AM2 and AM2

PDF	34 Pages

Scroll/Zoom	100%

nhà sản xuất	FINTEK [Feature Integration Technology Inc.]

Trang chủ	http://www.fintek.com.tw/eng

Logo

9 / 34 page

Fintek

Feature Integration Technology Inc.

V0.16P

F75125

4 Pin Description

4.1. Power Pin

Pin No.

Pin Name

Type

Description

VSB3V

3.3V stand by power

VDDA

VDDA input

VDDIO

VDDIO power

VSS

Ground

4.2. North Bridge Voltage Pin/ Voltage Regulator Set Trap Pin

Pin No.

Pin Name

Type

PWR

Description

VREF_NB

AOUT

VSB3V

In PVI output mode, reference voltage output to external

single phase PWM to supply VNB.

NB_EN#/VR_TRAP

O12

VSB3V

Pull high to 3,3VSB before POK, the F75125 will enter SVI

output mode, or the F75125 is set to PVI output mode.

In PVI output mode, NB_EN# is an external single phase

PWM enable signal.

Power pins

INst

TTL level input pin with schmitt trigger

INLV

Low level input, transient point at 0.9V

I/OD12st5V - TTL level bi-directional pin with schmitt trigger, Open-drain output with 12 mA sink

capability, 5V tolerance

I/OD12st

- TTL level bi-directional pin with schmitt trigger, Open-drain output with 12 mA sink

capability.

I/OD12LV

Low level input, transient point at 0.9V , Open-drain output with 12 mA sink capability

O12

- Output pin with 12mA sink/driving

capability.

OD12

- Open-Drain output pin with 12mA sink capability.

AIN

- Input pin (Analog).

AOUT

- Output pin (Analog).

F75125 bảng dữ liệu(PDF) 9 Page - Feature Integration Technology Inc.

F75125 bảng dữ liệu(HTML) 9 Page - Feature Integration Technology Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

bảng dữ liệu tải về

Link URL