STM8L151C4U6 datasheet(79/122 Pages) STMICROELECTRONICS

79 / 122 page

STM8L151xx, STM8L152xx

Electrical parameters

Doc ID 15962 Rev 5

79/122

9.3.4

Clock and timing characteristics

HSE external clock (HSEBYP = 1 in CLK_ECKCR)

Subject to general operating conditions for VDD and TA.

LSE external clock (LSEBYP=1 in CLK_ECKCR)

Subject to general operating conditions for VDD and TA.

Table 27.

Current consumption under external reset

Symbol

Parameter

Conditions

Typ

Unit

IDD(RST)

Supply current under

external reset (1)

All pins are externally

tied to VDD

VDD = 1.8 V

µA

VDD = 3 V

VDD = 3.6 V

All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.

Table 28.

HSE external clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fHSE_ext

External clock source

frequency(1)

Guaranteed by design, not tested in production.

116

MHz

VHSEH

(2)

Data based on characterization results, not tested in production.

OSC_IN input pin high level

voltage

0.7 x VDD

VDD

VHSEL

(2)

OSC_IN input pin low level

voltage

VSS

0.3 x VDD

Cin(HSE)

OSC_IN input

capacitance(1)

2.6

ILEAK_HSE

OSC_IN input leakage

current

VSS < VIN < VDD

±1

µA

Table 29.

LSE external clock characteristics

Symbol

Parameter

Min

Typ

Max

Unit

fLSE_ext

External clock source frequency(1)

32.768

kHz

VLSEH

(2)

OSC32_IN input pin high level voltage

0.7 x VDD

VDD

VLSEL

(2)

OSC32_IN input pin low level voltage

VSS

0.3 x VDD

Cin(LSE)

OSC32_IN input capacitance(1)

0.6

ILEAK_LSE

OSC32_IN input leakage current

±1

µA

Guaranteed by design, not tested in production.

Data based on characterization results, not tested in production.

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