FX929AD2 datasheet(21/44 Pages) CMLMICRO

21 / 44 page

4-Level FSK Modem Data Pump

FX929A

D/929A/4

Modem Rx input

Symbols to

De-interleave circuit

Data from Data Block Buffer

Task to Command Register

for task #1

for task #2

for task #3

BFREE bit

Figure 11 Receive Task Timing Diagram

Task

Time

(symbol times)

Time to receive all symbols of task

SFS

25 (minimum)

SFP

48 (minimum)

RSID

RHB/RILB

R4S

Maximum time between first symbol of task

SFS

entering the de-interleave circuit and the

SFP

task being written to modem.

RSID

RHB/RILB

R4S

Maximum time from the last bit of the task

Any

entering the de-interleave circuit to BFREE

going to a logic '1' (high)

RRC Filter Delay

The previous task timing figures are based on the signal at the input to the RRC filter (in transmit mode) or the

input to the de-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times through

to the RRC filter in both transmit and receive modes, as illustrated below:

Symbol-times

Tx Symbol to RRC Filter

Rx Symbo l to D e-int erleave Buffer

Tx Symbol at Txop pin / Rx Symbo l from FM discriminator

Figure 12 RRC Low Pass Filter Delay

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