FX929AD2 datasheet(32/44 Pages) CMLMICRO

32 / 44 page

4-Level FSK Modem Data Pump

FX929A

D/929A/4

1.6.2

Receive Frame Examples

The operations needed to receive a single Frame consisting of Symbol and Frame Sync sequences, Station ID

block and one each Header, Intermediate and Last blocks are shown below;

Ensure that the Control Register has been loaded with suitable CKDIV, FSTOL, LEVRES and

PLLBW valus, and that the IRQNEN bit of the Mode Register is '1', the TXRXN, RXEYE, PSAVE and

SSIEN bits are '0', and the INVSYM bit is set appropriately.

Wait until the received carrier has been present for at least 8 symbol times (see Section 1.6.3).

Read the Status Register to ensure that the BFREE bit is '1'.

Write a byte containing a SFP task with the AQSC and AQLEV bits set to '1' to the Command

Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be

'1' and the CRCERR and DIBOVF bits should be '0'.

Read 3 Station ID bytes from the Data Block Buffer.

Write a RHB task to the Command Register.

Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be

'1' and the DIBOVF bit '0'.

Check that the CRCERR bit of the Status Register is '0' and read 10 Header Block bytes from the

Data Block Buffer.

Write a RILB task to the Command Register.

11.

Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be

'1' and the DIBOVF bit '0'.

12.

Read 12 Intermediate Block bytes from the Data Block Buffer.

13.

Write a RILB task to the Command Register.

14.

Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be

'1' and the DIBOVF bit '0'.

15.

Check that the CRCERR bit of the Status Register is '0' and read the 8 Last Block bytes from Data

Buffer.

Note: The value of the latest 'S' symbol received will be contained in the SVAL bits each time that the Status

every 'S' symbol is received - in which case the µC will have to distinguish between interrupts caused by the

BFREE bit going to '1', and those caused by the SRDY bit being set to '1'.

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