AT89LP51 datasheet(30/113 Pages) ATMEL

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3709B–MICRO–12/10

AT89LP51/52 - Preliminary

6.4

System Clock Divider

The CDV

2-0 bits in CLKREG allow the system clock to be divided down from the selected clock

source by powers of 2. The clock divider provides users with a greater frequency range when

using the Internal Oscillator. For example, to achieve a 230.4 kHz system frequency when using

the RC oscillator, CDV

2-0 should be set to 011B for divide-by-8 operation. The divider can also

be used to reduce power consumption by decreasing the operational frequency during non-criti-

cal periods. The resulting system frequency is given by the following equation:

where f

OSC is the frequency of the selected clock source. The clock divider will prescale the clock

for the CPU and all peripherals. The value of CDV may be changed at any time without interrupt-

ing normal execution. Changes to CDV are synchronized such that the system clock will not

pass through intermediate frequencies. When CDV is updated, the new frequency will take

affect within a maximum period of 32 x t

OSC.

In Compatibility mode the divider defaults to divide-by-2 and and in Fast mode it defaults to no

division.

Note:

The reset value of CLKREG is 0000000B in Fast mode and 01010010B in Compatibility mode.

fSYS

OSC

CDV

-------------

Table 6-2.

CLKREG

– Clock Control Register

CLKREG = 8FH

Reset Value = 0?0? 00?0B

Not Bit Addressable

TPS3TPS2TPS1TPS0

CDV2

CDV1

CDV0

—

Bit

543

Symbol

Function

TPS[3-0]

Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1, Timer 2 and the Watchdog Timer. The

prescaler is implemented as a 4-bit binary down counter. When the counter reaches zero it is reloaded with the value

stored in the TPS bits to give a division ratio between 1 and 16. By default the timers will count every clock cycle in Fast

mode (TPS = 0000B) and every six cycles in Compatibility mode (TPS = 0101B).

CDV[2-0]

System Clock Division. Determines the frequency of the system clock relative to the oscillator clock source.

CDIV2

CDIV1

CDIV0

System Clock Frequency

000fOSC/1

001fOSC/2

010f

OSC/4

011fOSC/8

100fOSC/16

101f

OSC/32

110Reserved

111Reserved

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