AT89LP51 datasheet(89/113 Pages) ATMEL

89 / 113 page

3709B–MICRO–12/10

AT89LP51/52 - Preliminary

Figure 17-11. In-System Programming (ISP) Start Sequence

17.9.4

ISP Exit Sequence

Execute this sequence to exit ISP mode and resume CPU execution mode.

Drive SCK low.

Wait at least t

SSD.

Tristate MOSI.

Wait at least t

RHZ and bring RST low.

Wait t

SSZ and tristate SCK.

Figure 17-12. In-System Programming (ISP) Exit Sequence

Note:

The waveforms on this page are not to scale.

17.9.5

Serial Peripheral Interface

The Serial Peripheral Interface (SPI) is a byte-oriented full-duplex synchronous serial communi-

cation channel. During In-System Programming, the programmer always acts as the SPI master

and the target device always acts as the SPI slave. The target device receives serial data on

MOSI and outputs serial data on MISO. The Programming Interface implements a standard

SPI Port with a fixed data order and For In-System Programming, bytes are transferred MSB

first as shown in Figure 17-13. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0,

CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of

SCK. For more detailed timing information see Figure 17-14.

tSTL

VDD

RST

SCK

HIGH Z

MOSI

HIGH Z

MISO

XTAL1

tRLZ

tZSS

tSSE

VDD

RST

SCK

HIGH Z

MOSI

HIGH Z

MISO

XTAL1

tSSZ

tSSD

tRHZ

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