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MPC8535E bảng dữ liệu(PDF) 125 Page - Freescale Semiconductor, Inc |
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MPC8535E bảng dữ liệu(HTML) 125 Page - Freescale Semiconductor, Inc |
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125 / 126 page ![]() Mechanical Dimensions of the MPC8535E FC-PBGA MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 125 3. Maximum solder ball diameter measured parallel to datum A 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Capacitors may not be present on all devices 6. Caution must be taken not to short exposed metal capacitor pads on package top. 7. All dimensions are symmetric across the package center lines, unless dimensioned otherwise. 6 Product Documentation The following documents are required for a complete description of the device and are needed to design properly with the part. • MPC8536E PowerQUICC III Integrated Processor Reference Manual (document number: MPC8536ERM) • e500 PowerPC Core Reference Manual (document number: E500CORERM) 7 Document Revision History Table 85 provides a revision history for the MPC8535E hardware specification. Table 85. Document Revision History Revision Date Substantive Change(s) 3 11/2010 • In Table 1, “MPC8535E Pinout Listing,” added the following note: “For systems that boot from Local Bus(GPCM)-controlled NOR flash or (FCM) controlled NAND flash, a pullup on LGPL4 is required...” In addition, updated footnote 26 and added footnote 29 to PCI1_AD. • Updated Table 21 • Updated Figure 25, “RGMII and RTBI AC Timing and Multiplexing Diagrams.” •In Table 44, “MII Management DC Electrical Characteristics,” changed the Voh/Vol values for MDIO/MDC. • Added Note 6 regarding USB n_DIR pin to Table 47, “USB General Timing Parameters6.” •In Table 64, “I2C AC Electrical Specifications,” updated footnote 2. •In Table 82, , Table 83, , Table 84, added the Revision Level A for Rev 1.2 2 09/2009 Note: •In Section 1, “Pin Assignments and Reset States,”updated the first sentence of the note to say, “The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration.” •In Table 40, “SGMII DC Receiver Electrical Characteristics,” changed LSTSAB to LSTSA and LSTSEF to LSTSE for Note 4. • Updated Die value and Bump/Underfill value in Table 84 Note: Updated Figure 81, “Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8535E FC-PBGA,” and its notes. 1 09/2009 • In Table 3, “Recommended Operating Conditions,” for VDD_CORE, removed 1.1 ± 55 mV. •In Table 5, “MPC8535E Power Dissipation 5,” remove note 5. •In Table 5, ”MPC8535E Power Dissipation 5,” changed an “—”’ to “0.” 0 08/2009 • Initial public release. |
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