MPC8535E datasheet(38/126 Pages) FREESCALE

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MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3

eSPI

Freescale Semiconductor

Figure 12 provides the AC test load for the SPI.

Figure 12. SPI AC Test Load

Figure 13 represent the AC timing from Table 21. Note that although the specifications generally reference the rising edge of

the clock, these AC timing diagrams also apply when the falling edge is the active edge.

Figure 13 shows the SPI timing in Master mode (internal clock).

Figure 13. SPI AC Timing in Master mode (Internal Clock) Diagram

SPI_CS outputs—Master data delay

tNIKHOV2

—6.0

—

SPI inputs—Master data input setup time

tNIIVKH

5—

—

SPI inputs—Master data input hold time

tNIIXKH

0—

—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from

the high state (H) until outputs (O) are valid (V).

3. SPCOM[RxDelay] is set to 0.

4. SPCOM[RxDelay] is set to 1.

Table 21. SPI AC Timing Specifications1 (continued)

Characteristic

Symbol 2

Min

Max

Unit

Note

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

SPICLK (output)

tNIIXKH

tNIKHOV

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

tNIIVKH

tNIKHOX

Output Signals:

SPI_CS[0:3]

(See Note)

tNIKHOV2

tNIKHOX2

Note: The clock edge is selectable on SPI.

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