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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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KMPC8567CVTAUGGA bảng dữ liệu(PDF) 85 Page - Freescale Semiconductor, Inc |
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KMPC8567CVTAUGGA bảng dữ liệu(HTML) 85 Page - Freescale Semiconductor, Inc |
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85 / 139 page  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 85 Serial RapidIO Table 62. Receiver AC Timing Specifications—2.5 GBaud Characteristic Symbol Range Unit Notes Min Max Differential Input Voltage VIN 200 1600 mV p-p Measured at receiver Deterministic Jitter Tolerance JD 0.37 — UI p-p Measured at receiver Combined Deterministic and Random Jitter Tolerance JDR 0.55 — UI p-p Measured at receiver Total Jitter Tolerance1 JT 0.65 — UI p-p Measured at receiver Multiple Input Skew SMI — 24 ns Skew at the receiver input between lanes of a multilane link Bit Error Rate BER — 10–12 —— Unit Interval UI 400 400 ps +/– 100 ppm Note: 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 54. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. Table 63. Receiver AC Timing Specifications—3.125 GBaud Characteristic Symbol Range Unit Notes Min Max Differential Input Voltage VIN 200 1600 mV p-p Measured at receiver Deterministic Jitter Tolerance JD 0.37 — UI p-p Measured at receiver Combined Deterministic and Random Jitter Tolerance JDR 0.55 — UI p-p Measured at receiver Total Jitter Tolerance1 JT 0.65 — UI p-p Measured at receiver Multiple Input Skew SMI — 22 ns Skew at the receiver input between lanes of a multilane link Bit Error Rate BER — 10-12 —— Unit Interval UI 320 320 ps +/- 100 ppm Note: 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 54. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. |
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