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KMPC8567CVTAUGGA bảng dữ liệu(PDF) 83 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications
PDF  139 Pages
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KMPC8567CVTAUGGA bảng dữ liệu(HTML) 83 Page - Freescale Semiconductor, Inc

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
83
Serial RapidIO
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the
transmitter shall fall entirely within the unshaded portion of the Transmitter Output Compliance Mask
shown in Figure 53 with the parameters specified in Table 60 when measured at the output pins of the
device and the device is driving a 100 Ohm +/–5% differential resistive load. The output eye pattern of an
LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol
interference) need only comply with the Transmitter Output Compliance Mask when pre-emphasis is
disabled or minimized.
Figure 53. Transmitter Output Compliance Mask
Table 59. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
VO
–0.40
2.30
Volts
Voltage relative to COMMON
of either signal comprising a
differential pair
Differential Output Voltage
VDIFFPP
800
1600
mV p-p
—
Deterministic Jitter
JD
—
0.17
UI p-p
—
Total Jitter
JT
—0.35
UI p-p
—
Multiple output skew
SMO
—
1000
ps
Skew at the transmitter output
between lanes of a multilane
link
Unit Interval
UI
320
320
ps
+/– 100 ppm
0
VDIFF min
VDIFF max
-VDIFF min
-VDIFF max
0B
1-B
1
Time in UI
A1-A



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