R27 datasheet(46/487 Pages) RENESAS

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R8C/26 Group, R8C/27 Group

5. Resets

Rev.2.10

Sep 26, 2008

Page 27 of 453

REJ09B0278-0210

Figure 5.5

OFS Register

Option Function Select Register

(1)

Symbol

Address

When Shipping

OFS

0FFFFh

FFh(3)

Bit Symbol

Bit Name

Function

NOTES:

CSPROINI

Count source protect

mode after reset select

bit

0 : Count source protect mode enabled after reset

1 : Count source protect mode disabled after reset

LVD1ON

Voltage detection 1

circuit start bit(5, 6)

0 : Voltage monitor 1 reset enabled after hardw are

reset

1 : Voltage monitor 1 reset disabled after hardw are

reset

ROMCP1

ROM code protect bit

0 : ROM code protect enabled

1 : ROM code protect disabled

ROMCR

ROM code protect

disabled bit

0 : ROM code protect disabled

1 : ROMCP1 enabled

—

(b1)

Reserved bit

Set to 1.

WDTON

Watchdog timer start

select bit

0 : Starts w atchdog timer automatically after reset

1 : Watchdog timer is inactive after reset

b7 b6 b5 b4 b3 b2 b1 b0

—

(b4)

Reserved bit

Set to 1.

LVD0ON

Voltage detection 0

circuit start bit(2, 4)

0 : Voltage monitor 0 reset enabled after hardw are

reset

1 : Voltage monitor 0 reset disabled after hardw are

reset

For N, D version only. For J, K version, set the LVD0ON bit to 1 (voltage monitor 0 reset disabled after hardw are

reset).

The LVD1ON bit setting is valid only by a hardw are reset. When the pow er-on reset function is used, set the

LVD1ON bit to 0 (voltage monitor 1 reset enabled after hardw are reset).

For J, K version only. For N, D version, set the LVD1ON bit to 1 (voltage monitor 1 reset disabled after hardw are

reset).

The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not

w rite additions to the OFS register.

If the block including the OFS register is erased, FFh is set to the OFS register.

The LVD0ON bit setting is valid only by a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0

(voltage monitor 0 reset enabled after hardw are reset).

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