PSD813F2V datasheet(13/109 Pages) STMICROELECTRONICS

13 / 109 page

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PSD813F2V, PSD854F2V

Doc ID 10552 Rev 3

Note: 1. The pin numbers in this table are for the PLCC package only. See the package information from Table 75., page 105 and Table

77., page 107 for pin numbers on other package types.

2. These functions can be multiplexed with other functions.

PC7

I/O

PC7 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC7) output.

Input to the PLDs.

DBE – active Low Data Byte Enable input from 68HC912 type MCUs.

This pin can be configured as a CMOS or Open Drain output.

PD0

I/O

PD0 pin of Port D. This port pin can be configured to have the following functions:

ALE/AS input latches address output from the MCU.

MCU I/O – write or read from a standard output or input port.

Input to the PLDs.

CPLD output (External Chip Select).

PD1

I/O

PD1 pin of Port D. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

Input to the PLDs.

CPLD output (External Chip Select).

CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and

the CPLD AND Array.

PD2

I/O

PD2 pin of Port D. This port pin can be configured to have the following functions:

MCU I/O - write to or read from a standard output or input port.

Input to the PLDs.

CPLD output (External Chip Select).

PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O.

When High, the PSD memory blocks are disabled to conserve power.

VCC

15, 38

Supply Voltage

GND

1, 16,

Ground pins

Pin Name

Type

Description

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