IXP45X datasheet(64/148 Pages) INTEL

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August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

ETHC_RXCLK

Externally supplied receive clock.

• 25 MHz for 100 Mbps operation

• 2.5 MHz for 10 Mbps operation

This MAC contains hardware hashing capabilities local to the interface.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system or when in

SMII mode of operation.

ETHC_RXDATA[3:1]

Receive data bus from PHY, data sampled synchronously, with respect to ETHC_RXCLK. This MAC

contains hardware hashing capabilities local to the interface.

• Not used when operating in SMII mode of operation.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system or when in

SMII mode of operation.

ETHC_RXDATA[0] /

SMII_RXDATA[5]

ZVI

MII Mode of Operation:

Receive data bus from PHY, data sampled synchronously, with respect to ETHC_RXCLK. This MAC

contains hardware hashing capabilities local to the interface

SMII Mode of Operation:

The data on this signal is received synchronously with respect to the rising edge of SMII_CLK

when operating as an SMII interface and synchronously with respect to the rising edge of

SMII_RXCLK when operating as a Source Synchronous SMII interface

Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

ETHC_RXDV

Receive data valid, used to inform the MII interface that the Ethernet PHY is sending data.

This MAC contains hardware hashing capabilities local to the interface.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

Table 15.

MII/SMII Interfaces (Sheet 6 of 7)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

††

Please refer to Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired

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