PSD813F1A datasheet(79/111 Pages) STMICROELECTRONICS

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PSD813F1A

Note: 1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.

2. CSI deselected or internal Power-down mode is active.

3. PLD is in non-Turbo mode, and none of the inputs are switching.

4. Please see Figure 36., page 73 for the PLD current calculation.

5. IOUT = 0mA

Table 46. DC Characteristics (3V devices)

VIH1

Reset High Level Input Voltage

(Note 1)

0.8VCC

VCC +0.5

VIL1

Reset Low Level Input Voltage

(Note 1)

–0.5

0.2VCC –0.1

VHYS

Reset Pin Hysteresis

0.3

VLKO

VCC (min) for Flash Erase and

Program

2.5

4.2

VOL

Output Low Voltage

IOL = 20µA, VCC = 4.5V

0.01

0.1

IOL = 8mA, VCC = 4.5V

0.25

0.45

VOH

Output High Voltage

IOH = –20µA, VCC = 4.5V

4.4

4.49

IOH = –2mA, VCC = 4.5V

2.4

3.9

ISB

Standby Supply Current

for Power-down Mode

CSI >VCC –0.3V (Notes

2,3)

200

µA

ILI

Input Leakage Current

VSS < VIN < VCC

–1

±0.1

µA

ILO

Output Leakage Current

0.45 < VOUT < VCC

–10

±5

µA

ICC (DC)

(Note 5)

Operating

Supply

Current

ZPLD Only

ZPLD_TURBO = Off,

f = 0MHz (Note 5)

0mA

ZPLD_TURBO = On,

f = 0MHz

400

700

µA/PT

Flash memory

or EEPROM

During Flash memory or

EEPROM WRITE/Erase

Only

Read only, f = 0MHz

SRAM

f = 0MHz

ICC (AC)

(Note 5)

ZPLD AC Adder

See Figure

36, note 4

Flash memory or EEPROM AC

Adder

2.5

3.5

mA/

MHz

SRAM AC Adder

1.5

3.0

mA/

MHz

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

VIH

High Level Input Voltage

3.0V < VCC < 3.6V

0.7VCC

VCC +0.5

VIL

Low Level Input Voltage

3.0V < VCC < 3.6V

–0.5

0.8

VIH1

Reset High Level Input Voltage

(Note 1)

0.8VCC

VCC +0.5

VIL1

Reset Low Level Input Voltage

(Note 1)

–0.5

0.2VCC –0.1

Symbol

Parameter

Test Condition (in addition

to those in Table 39)

Min.

Typ.

Max.

Unit

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