910GL datasheet(130/426 Pages) INTEL

130 / 426 page

Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

130

Datasheet

Bit

Access &

Default

Description

R/W

Bus Master Enable (BME): This bit does not affect forwarding of completions

from the primary interface to the secondary interface.

0 = This device is prevented from making memory or I/O requests to its primary

bus. Note that according to the PCI specification, as MSI interrupt messages

are in-band memory writes, disabling the bus master enable bit prevents this

device from generating MSI interrupt messages or passing them from its

secondary bus to its primary bus. Upstream memory writes/reads, I/O

writes/reads, peer writes/reads, and MSIs will all be treated as illegal cycles.

Writes are forwarded to memory address 0h with byte enables de-asserted.

Reads will be forwarded to memory address 0h and will return Unsupported

Request status (or Master abort) in its completion packet.

1 = This device is allowed to issue requests to its primary bus. Completions for

previously issued memory read requests on the primary bus will be issued

when the data is available.

R/W

Memory Access Enable (MAE)

0 = All of device 1’s memory space is disabled.

1 = Enable the Memory and Pre-fetchable memory address ranges defined in the

MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.

R/W

IO Access Enable (IOAE)

0 = All of device 1’s I/O space is disabled.

1 = Enable the I/O address range defined in the IOBASE1 and IOLIMIT1

registers.

8.1.4

PCISTS1—PCI Status (D1:F0)

PCI Device:

Address Offset:

06h

Default Value:

0000h

Access:

RO, R/W/C

Size:

16 bits

This register reports the occurrence of error conditions associated with primary side of the

“virtual” Host-PCI Express bridge in the (G)MCH.

Bit

Access &

Default

Description

Detected Parity Error (DPE): Hardwired to 0. Parity (generating poisoned TLPs)

is not supported on the primary side of this device.

R/WC

Signaled System Error (SSE):

1 = This bit is set when this Device sends an SERR due to detecting an

ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the

Command register is ‘1’. Both received (if enabled by BCTRL1[1]) and

internally detected error messages do not affect this field.

Received Master Abort Status (RMAS): Not Applicable or Implemented.

Hardwired to 0. The concept of a master abort does not exist on primary side of

this device.

910GL bảng dữ liệu(PDF) 130 Page - Intel Corporation

910GL bảng dữ liệu(HTML) 130 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL