TDF8591TH datasheet(12/34 Pages) NXP

12 / 34 page

TDF8591TH_1

Product data sheet

Rev. 01 — 5 March 2008

12 of 34

NXP Semiconductors

TDF8591TH

× 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D ampliﬁer

[1]

The circuit is DC adjusted at VP = ±12.5 V to ±30 V.

[2]

Refers to usage in a symmetrical supply application (see Section 12.7). In an asymmetrical supply application the SGND voltage should

be deﬁned by an external circuit.

[3]

The transition between Standby and Mute mode contains hysteresis, while the slope of the transition between Mute and Operating

mode is determined by the time constant on pin MODE (see Figure 9).

[4]

Pin DIAG should not be connected to an external pull-up.

[5]

DC output offset voltage is applied to the output during the transition between Mute and Operating mode in a gradual way. The

dVO(offset)/dt caused by any DC output offset is determined by the time constant on pin MODE.

[6]

At a junction temperature of approximately Tact(th_fold) − 5 °C the gain reduction will commence and at a junction temperature of

approximately Tact(th_fold) + 5 °C the ampliﬁer mutes.

Ampliﬁer outputs; pins OUT1 and OUT2

VO(offset)

output offset voltage

SE; mute

SE; operating

[5] -

170

BTL; mute

BTL; operating

[5] -

240

Stabilizer output; pin STABI (reference to VSSP1)

output voltage

mute and operating; with respect

to VSSD

12.5

Temperature protection

Tprot

protection temperature

160

180

°C

Tact(th_fold)

thermal foldback activation

temperature

closed loop SE voltage gain

reduced with 6 dB

[6] 145

150

°C

Table 7.

Static characteristics …continued

VP = ±27 V; fosc = 310 kHz; Tamb = −40 °C to +85 °C; Tj = −40 °C to +150 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Fig 9.

Behavior of pin MODE

STBY

MUTE

5.5

001aad842

VMODE (V)

4.2

2.8

2.2

0.8

VO(offset)

mute

operating

slope is directly related to the

time constant on pin MODE

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